A conventional latched comparator has two input signals and outputs a decision regarding the relative value of the input signals every comparator clock cycle. For example, assuming one of the inputs is a reference signal, when the non-reference input signal value is greater than the reference signal value, the output decision of the comparator is high, and when the non-reference input signal value is less than the reference signal value the output decision of the comparator is low. When the signal and reference values are equal, the comparator output enters an unpredictable state. In practice, with equal inputs, the output will dither between low and high values due to noise with high and low output values being equally probable. When the input signal value deviates from the reference signal value, the probabilities of high and low output states increase or decrease with a normal probability distribution function characterized, in some circuits, by a standard deviation equal to the input referred noise Root Mean Square (RMS) value.
In addition to noise, a comparator device can be affected by systematic and/or random unbalancing factors, so that even in the case of equal inputs, the output decisions are not evenly distributed between high and low states. These unbalancing factors can be static or dynamic. Static unbalancing factors can include offset voltages resulting from unequal threshold voltages (e.g., in CMOS related technologies), or unequal currents flowing through various circuit branches, or unequal physical dimensions of transistors.
Dynamic unbalancing factors can include unbalanced charges in the channels of transistors used as switches in the comparator chain. These unbalanced charges can be injected in various nodes into the comparator chain when the switches are turned off. Additionally, unbalanced charge transfer can occur in transistors used in feedback circuitry associated with a track-and-latch stage of a comparator chain. Due to static and dynamic unbalancing factors, a comparator device may not output a balanced probability of high and low output states when the input signals are equal. Unbalancing factors become even more problematic in practical realizations of comparator chains that include one or more preamplifier stages followed by a track-and-latch comparator or decision stage. Each stage in the comparator chain can be affected by unbalancing factors that can contribute to offsets. Accordingly, it is possible that the main contributors of static and dynamic unbalancing factors, although having unpredictable values, are fixed once a circuit is fabricated, since solid state circuits, and therefore the associated unbalancing factors, tend not to change during normal circuit operation.
There are also time variant unbalancing factors which can appear in a comparator chain. Generally, time variant unbalancing factors are random in nature and can be attributed to noise which adds to the input noise and noise generated by solid state circuit elements in the comparator chain.